1. Field of the Invention
The present invention relates to routing in an electronic device, particularly with respect to programmable logic devices.
2. Description of Related Art
Programmable logic devices (“PLDs”) (also sometimes referred to as CPLDs, PALs, PLAs, FPLAs, EPLDs, EEPLDs, LCAs, FPGAs, or by other names), are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices are well known in the art and typically provide an “off the shelf” device having at least a portion that can be programmed to meet a user's specific needs. Application specific integrated circuits (“ASICs”) have traditionally been fixed integrated circuits, however, it is possible to provide an ASIC that has a portion or portions that are programmable; thus, it is possible for an integrated circuit device to have qualities of both an ASIC and a PLD. The term PLD as used herein will be considered broad enough to include such devices.
PLDs have configuration elements that may be programmed or reprogrammed. Configuration elements may be realized as RAM bits, flip-flops, EEPROM cells, or other memory elements. Placing new data into the configuration elements programs or reprograms the PLD's logic functions and associated routing pathways. Configuration elements that are field programmable are often implemented as RAM cells (sometimes referred to a “CRAM” or “configuration RAM”). However, many types of configurable elements may be used including static or dynamic random access memory, electrically erasable read-only memory, flash, fuse, and anti-fuse programmable connections. The programming of configuration elements could also be implemented through mask programming during fabrication of the device. While mask programming may have disadvantages relative to some of the field programmable options already listed, it may be useful in certain high volume applications.
PLDs typically include blocks of logic elements, sometimes referred to as logic array blocks (“LABs”; also referred to by other names, e.g., “configurable logic blocks,” or “CLBs”). Logic elements (“LEs”, also referred to by other names, e.g., “logic cells”) may include a look-up table (LUT) or product term, carry-out chain, register, and other elements. LABs (comprising multiple LEs) may be connected to horizontal and vertical conductors (“H-lines” and “V-lines”) that may or may not extend the length of the PLD's core.
As core density and complexity increases and as the volume of signals processed by a device grows, it is increasingly important to provide flexibility in core signal routing. A PLD core may include routing resources (e.g. H-lines and V-lines) having a variety of logical lengths (measured relative to logic regions spanned) for routing between logic regions (e.g. LABs) and for routing between core and I/O regions. However, in some instances, core routing lines that are relatively longer in length may be fewer in number than shorter length lines. Generally, in order to provide increased flexibility for routing onto the lines, the size of a multiplexer (“mux”) or muxes feeding line drivers must be increased. However, if there is a desire to provide access to several additional resources (e.g. other routing resources trying to route onto the line), increasing the line's mux (or muxes) by one input for each additional resource can be detrimental both due to increased line loading and the increased space costs for a larger mux.
At the same time, muxes used to route signals into LABs (or other types of circuit regions) and into individual LEs (or other types of sub-regions) are not always fully utilized. These muxes provide a potential resource whose excess flexibility may be utilized to provide increased flexibility for routing onto particular lines without unduly increasing the size of those muxes that directly feed the particular line.
Thus there is both a need and an opportunity to provide routing connections that increase the number of resources that can access a particular routing line without unduly increasing the size of the mux feeding that line.